Senior AE Group Director

Cadence Design Systems•San Jose, CA

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Sr. Group Director – Memory and Serdes Applications Position Overview Cadence is seeking a motivated, detail-oriented, and creative leader to join the North America IP Sales team as the Senior Director of Applications Engineering for our Design IP portfolio. The ideal candidate is an experienced High-Speed Interface Technologist who excels at leading multiple teams of skilled engineers and collaborating with customers to develop solutions for their System/ASIC/SoC designs using the Cadence Serdes and memory IP portfolio. This is a pre-sales role, well-suited for someone with System/ASIC/SoC design experience, strong interpersonal and communication skills, and a commitment to ensuring customer success. The position offers the opportunity to work across various market segments, including AI, Cloud, Networking, and Storage, as well as designs, foundries, and leading-edge processes. The successful candidate will build credibility by addressing the most challenging high-speed interface and memory problems.

Requirements

MSEE with 20+ years of relevant experience, or PhD with 15+ years of relevant experience.
Management experience leading a highly technical team.
Previous experience in selecting, using, designing, or supporting PHY and controller interface IP, internally or externally.
Understanding of the latest SoC architectures and system-level design practices for market segments such as AI, HPC, mobile, storage, automotive, networking, and IoT, with a particular focus on IP requirements.
Prior experience and knowledge of one or more interface, memory, and connectivity protocols, including DDR, LPDDR, HBM, PCIe, CXL, UCIe, and Ethernet.
Familiarity with state-of-the-art SoC design implementation and development flow, including RTL design, synthesis and static timing analysis, physical design flow, testbench creation and simulation, some exposure to analog/mixed-signal design and verification flows, and basic knowledge of foundry, package, and PCB design flows and technologies.
Ability to understand and communicate complex technical requirements, challenges, and solutions clearly in both verbal and written formats.
Proven ability to organize, conduct, and coordinate meetings involving multiple internal and external teams.
Willingness to travel approximately 10% of the time to visit customers, sales teams, and engineering locations.

Nice To Haves

Prior IP or SoC design experience is highly desirable.

Responsibilities

Lead and mentor a high-performing team of senior application engineers focused on technical presales for high-speed interface PHYs and controllers.
Develop strategies to secure complex bundle IP and services deals that encompass memory, Serdes, and foundation IPs.
Establish the infrastructure and methodology necessary to integrate new IP acquisitions and drive efficiency improvements using AI.
Develop customer solutions by leveraging the broad Cadence IP portfolio.
Collaborate with sales and marketing teams to identify and understand customers’ technical and business challenges.
Educate customers on how Cadence's IP products address their requirements and assist them in evaluating the IP, with support from product R&D teams.
Influence the IP product development roadmap by communicating customer needs to product R&D teams.
Stay informed about industry trends and protocol evolutions at JEDEC, PCI-SIG, and other standards bodies.
Manage and support customer engagements through on-site or remote technical interactions, including providing demos, supporting evaluations, resolving technical issues, addressing competitive challenges, and regularly communicating status across cross-functional teams.