RTL Engineer

Samsung Semiconductor • San Jose, CA

9d • Onsite

About The Position

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for C-HBM component IPs including TSV interconnects. The role focuses on translating RTL/SystemC/C behavior into time-indexed, workload-aware power models calibrated against steady-state and worst-case anchors. The IP power macromodels will generate time-indexed power map for dynamic thermal analysis.
Location: Daily onsite presence at o ur San Jose, CA office in alignment with our Flexible Work policy
Reports to: SVP, R&D (Power & Thermal Lab)

Requirements

• Bachelors degree 5+ years of experience or Masters degree 3+ years of experience.
• Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
• Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
• Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
• Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
• Familiarity with SystemC or transaction-level modeling.
• Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
• Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Nice To Haves

• Experience with GPU, computer architecture, HBM, memory controllers, PHYs, or high-speed I/O.
• Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
• Exposure to low-power design and thermal management.
• Exposure to power macromodeling, power estimation flows, or architectural power analysis.

Responsibilities

• Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for HBM component IPs (PHY, controller, interconnects, training logic, TSV, etc.) using analytical modeling, LUT, FSM, NN, and their hybrid.
• Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
• Define power-relevant functional states (transaction/state-based abstraction).
• Support trace-driven power modeling, aligned with C/SystemC workload traces.
• Perform synthesis-assisted calibration using average and worst-case power anchors when available.
• Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
• Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
• Contribute to scalable IP-wise composition for full-system power simulation.

Benefits

• Medical/Dental/Vision/401k
• inclusive rewards plan empowers our people to care for their whole selves.
• charitable giving match
• 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
• a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
• on-demand apps and free confidential therapy sessions
• onsite Café and gym, plus virtual classes

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees