RTL Engineer, Ethernet

Eridu AI • Saratoga, CA

156d

About The Position

We are seeking an RTL Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. The candidate will be part of Design Group responsible for defining, specifying, architecting, executing and productizing leading-edge Networking devices.

Requirements

• Master’s degree in Electrical Engineering (MSEE) with 8-15 years of experience.
• Proven record of successful tape-outs and productization, preferably in networking devices.
• Strong understanding of the Ethernet 802.3 protocol, including framing, encoding, and broadcasting/unicasting; familiarity with Ultra Ethernet developments is preferred.
• Solid knowledge of SerDes fundamentals, including clocking, Decision Feedback Equalization (DFE), CTLE, and initialization.
• Comprehensive understanding of multiple clock, reset, and power domain design challenges with safe/robust design practices.
• Experience in refactoring and restructuring designs to address timing and area challenges, including algorithmic and structural design changes.
• Ability to optimize hardware versus firmware implementations for overall product performance and efficiency.
• Excellent knowledge of industry-standard tools and best-in-class practices for high-quality design.
• Prior experience with source synchronous design implementation.
• Essential knowledge of Ethernet architectures and Layer 2, Layer 3, and Layer 4 networking protocols.
• Prior experience in integrating a MAC IP with PCS and SerDes PHY, preferably at 100G or higher.
• Thorough understanding of the ASIC design flow, including requirements for DFT and physical implementation.

Responsibilities

• Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, including MAC, PCS, and SerDes.
• Perform RTL coding, conduct code reviews, and debug designs.
• Work with third-party vendors to procure and integrate the Ethernet block with MAC, PCS, and PHY.
• Partner with Verification Engineers to define the test plan, execute verification, and understand both serial and parallel mode VIP behavior.
• Debug the full Ethernet protocol stack.
• Engage in post-silicon activities such as bring-up, platform validation, characterization, parameter optimization, and final productization.
• Support the definition of development flows that improve execution efficiency and quality.
• Collaborate closely with Physical Design, Firmware, and Design Verification teams to ensure successful end-to-end RTL implementation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 11-50 employees