RTL Design Engineer

Apple-posted about 2 months ago
Melbourne, FL
5,001-10,000 employees
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At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and uncommonly hardworking RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, you will have the opportunity to specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side).

  • Specify and/or micro-architect digital blocks in advanced mixed-signal circuits with embedded micro-controller.
  • Design RTL coding of blocks specified by you or others.
  • Participate in the design verification and bring-up of blocks by writing RTL assertions and debugging code.
  • Interact with the design verification team.
  • Handle various front end methodology flows including pre-silicon power analysis, clock domain crossing, reset domain crossing, and unified power flow (UPF).
  • Participate in lab bring-up of circuits by writing test scripts, analyzing lab data, and proposing experiments.
  • BS degree in technical discipline.
  • Minimum 10 years of relevant experience.
  • Deep knowledge of mixed signal concepts.
  • Deep knowledge of RTL design fundamentals (control and data path).
  • Deep knowledge of Verilog and SystemVerilog.
  • Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers).
  • Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test).
  • Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques.
  • Deep knowledge of scripting languages; Perl and Python are plusses.
  • Deep knowledge of Algorithm developments.
  • Strong communication and presentation skills.
  • SERDES architecture knowledge is a plus.
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