RTL Design Engineer

AMD-posted 7 months ago
Mid Level
Santa Clara, CA
Computer and Electronic Product Manufacturing
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At AMD, we care deeply about transforming lives with our technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded systems. We are seeking a seasoned logic designer with expertise or significant interest in IP design and development. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features.

  • Define IP features and capabilities, close architecture, and micro-architecture requirements.
  • Drive technical specifications to meet requirements and provide technical direction to execution teams.
  • Participate in the development of Architecture and Micro-architecture specifications for the Logic components.
  • Work cross-functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions.
  • Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting DDR and LPDDR DRAM Technologies.
  • Deliver Designs that meet functional and performance requirements.
  • Deliver Design that meet physical/structural design constraints (timing, area, power).
  • Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bringup to coverage closure.
  • Work closely with SOC teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs.
  • Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.
  • Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: Memory sub-system, Fabrics, Encryption, Compression, Security.
  • Experience analyzing memory sub-system micro-architectural features to identify performance bottlenecks within different workloads and optimize power, performance, and area.
  • Strong desire to deliver high quality bug free designs all the way through the silicon development process.
  • Strong experience in Logic design implementation using hardware description language (RTL) with BSEE/MSEE.
  • Strong RTL analysis skills including Verilog or system Verilog, Timing Analysis and understanding of standard cell libraries.
  • Hands on experience in taping out cutting edge SOC including Post-Silicon Debug experience.
  • Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics.
  • Usage/execution of logic simulation, synthesis and familiarity with logic development flows.
  • Must be a self-starter, and be able to independently and efficiently drive tasks to completion.
  • Excellent analytical and problem solving skills along with attention to details.
  • Excellent communication, management, and presentation skills.
  • Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies.
  • AMD benefits at a glance.
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