RTL Design Engineer

Advanced Micro Devices, Inc.-posted about 1 month ago

Full-time • Mid Level

Hybrid • San Jose, CA

5,001-10,000 employees

Computer and Electronic Product Manufacturing

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At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join our leading-edge Design and RTL Methodology team as a Hardware Development Engineer, contributing directly to the development of our latest FPGA products. In this role, you will help ensure the highest quality of RTL design that our customers rely on. THE PERSON: You are an experienced, proactive RTL Design Engineer who thrives in a fast-paced environment. You quickly ramp up on new tools and methodologies, and you're comfortable working on a small, highly capable team where you can take on significant responsibility.

We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem.
Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.
Enhance and develop flows that analyze RTL and Unified Power Format (UPF) Files, including updating or creating new UPF to enable robust verification of power-domain crossings for AMD's next-generation monolithic and stacked FPGA-SoC product families.
You will also be responsible for enhancing flows that analyze RTL files and Unified Power Format (UPF) files and then updating or even creating new UPF files to enable extensive verification of power domain crossings for AMD's next generation monolithic and stacked FPGA-SoC product families.
Leverage corporate AI systems to increase productivity and streamline workflows.

Proven experience in logic design and static verification (SystemVerilog, Verilog, or VHDL), ideally with contributions to at least two ASIC products brought to market.
Strong background in RTL/logic design, including specifying multi-power-domain architectures using IEEE 1801 Unified Power Format (UPF).
Experience in RTL / logic design including specifying multi-power domain designs using IEEE 1801 Unified Power Format (UPF).
Programming skills in Perl, Python, and TCL.

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