RTL Design Engineer

Niobium•Dayton, OH

2d•Remote

About The Position

At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner for DoD and commercial customers whose solutions require lower power, higher efficiency, and proven security. Founded as a 2021 spinout from a world-class security and computing systems R&D company, our team combines decades of experience in advanced semiconductor design with experience in advanced cryptography. Niobium is headquartered in Dayton, Ohio with additional locations in Portland, Oregon; and Columbus, Ohio. We will not be limited by geography for the right candidate. Our values are at the heart of every decision we make and we understand that each member of our talented team is the key to our on-going success. For those reasons, we've designed a highly competitive benefits program to support employees and their families. These include: Competitive salaries Employer paid health care Employer contribution to health savings account Flexible time off Flexible work location with remote options 401K employer match POSITION DESCRIPTION / Niobium Microsystems is seeking SoC Engineers with 5 or more years of relevant industry experience. The ideal candidate has been involved in product designs in a production setting. Niobium’s Engineering team is seeking passionate and creative individuals with strong technical skills to join our expanding SoC team. As an SoC Engineer, you will work in a small talented team of SoC Engineers researching, designing, and implementing novel methodologies and architectures. You will have the opportunity to contribute to all areas of SoC design, verification, and implementation. Projects range from integrating third party IPs to designing complex systems.

Requirements

RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
Third Party IP Integration experience
Logic synthesis and static timing analysis
SoC design flow including chip-level design, block/IP design and behavioral modeling
Modeling SoC architectures with FPGAs
Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
Experience with RISC-V architecture
Working knowledge of PCIe and DDR
Clock domain crossing methodologies
Scripting languages such as Python, Perl, Tcl, shell, etc.
Strong familiarity with EDA tools
Strong problem solving and debugging capabilities