RTL Design Engineer

Advanced Micro Devices, Inc.•San Jose, CA

48d•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Adaptive and Embedded Computing Group, you will help bring to life cutting-edge designs.â As a member of the front-end design team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex processor architecture, RTL coding, and digital design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Requirements

Strong front-end RTL engineering background
Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers
Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments
Experience with Arm architecture and APB, AXI, CHI protocols
Experience with design reuse, including RTL, constraints, and waivers
Experience with SoC level design integration
Experience with automation using scripting techniques such as PERL, Python, or Tcl
Experience with timing constraints and timing exceptions
Experience running standard quality checks such as LINT and CDC
Experience designing with multiple power domains including writing UPF
Must be a self-starter and self-motivated

Responsibilities

Own the design and implementation of blocks to meet functional, timing, area and power requirements
Guide and review verification for these blocks
Design and implement logic functions that enable efficient test and debug
Implement automation to increase design team efficiency