Arrow Electronics-posted 3 months ago
$160,000 - $180,000/Yr
Full-time • Senior
Santa Clara, CA
5,001-10,000 employees

The RTL Design Engineer role at eInfochips involves working with the Arteris Design Toolset and requires strong expertise in Verilog Design, particularly with AMBA AXI bus and ARM or C based processors. The engineer will ensure customer satisfaction by effectively reporting progress to customers and maintaining awareness of NOC Architecture. The position is remote but may require travel to client locations as needed.

  • Utilize Arteris Design Toolset for RTL design.
  • Design and implement Verilog components with a focus on PCIe physical layer requirements.
  • Ensure compliance with PCIe specifications including PIPE interface, LTSSM, and encoding standards.
  • Lead silicon bring-up activities and troubleshoot PCIe related issues.
  • Report daily or weekly progress to customers.
  • 10+ years of experience in RTL design.
  • 5+ years of experience in Verilog Design.
  • Deep understanding of PCIe system architecture and physical layer design.
  • Experience with SerDes technology and its integration into high-speed communication interfaces.
  • Bachelor's degree or equivalent training.
  • Experience with SystemVerilog.
  • Knowledge of ASIC design and development processes.
  • Medical, Dental, Vision Insurance
  • 401k with Matching Contributions
  • Short-Term/Long-Term Disability Insurance
  • Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
  • Paid Time Off (including sick, holiday, vacation, etc.)
  • Tuition Reimbursement
  • Growth Opportunities
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