The RTL Design Engineer at eInfochips will be responsible for designing, implementing, and verifying ASIC components with a focus on PCIe physical layer requirements. The role requires strong expertise in the Arteris Design Toolset and a deep understanding of PCIe system architecture, including compliance with specifications and troubleshooting related issues. The position is based in San Jose, CA, but allows for remote work, with the expectation of occasional travel to client locations as needed.