RTL Design Engineer (eInfochips)

Arrow Electronics

138d • $160,000 - $180,000

About The Position

The RTL Design Engineer at eInfochips will be responsible for designing, implementing, and verifying ASIC components with a focus on PCIe physical layer requirements. The role requires strong expertise in the Arteris Design Toolset and a deep understanding of PCIe system architecture, including compliance with specifications and troubleshooting related issues. The position is based in San Jose, CA, but allows for remote work, with the expectation of occasional travel to client locations as needed.

Requirements

• 10+ years of experience in RTL design.
• Bachelor's degree or equivalent training required.
• Extensive knowledge of SerDes technology and its integration into high-speed communication interfaces.

Nice To Haves

• Experience with PCIe retimer specification.
• NOC Architecture awareness.

Responsibilities

• Strong expertise on Arteris Design Toolset.
• At least 5+ years of experience in Verilog Design and AMBA AXI bus along with ARM or C based processor.
• Ensure customer satisfaction and report to customers on daily or weekly progress.
• Deep understanding and hands-on experience in PCIe system architecture.
• Ensure compliance with PCIe specifications, including PIPE interface, LTSSM, 8b/10b and 128b/130b encoding.
• Lead silicon bring-up activities and troubleshoot PCIe related issues.
• Design, implement, and verify ASIC components focusing on PCIe physical layer requirements.
• Utilize Verilog and SystemVerilog for development.

Benefits

• Medical, Dental, Vision Insurance.
• 401k with Matching Contributions.
• Short-Term/Long-Term Disability Insurance.
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options.
• Paid Time Off (including sick, holiday, vacation, etc.).
• Tuition Reimbursement.
• Growth Opportunities.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees