Research Scientist Intern, Silicon Performance Architecture (PhD)
About The Position
Reality Labs (RL) focuses on delivering Meta's vision through AI-first devices that leverage Mixed Reality (MR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Mixed and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & MR devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. We are seeking research interns with a background in Performance Modeling, Performance Simulation Methodologies, and Computer Architecture to improve our performance modeling collateral and use those models to guide the architecture of AR/MR silicon. Our internships are twelve (12) to twenty-four (24) weeks long and we have various start dates throughout the year.
Requirements
- Currently has, or is in the process of obtaining, a PhD in Computer Science, Electrical Engineering or related field
- Experience with programming in C/C++ and Python (scripting)
- Experience in computer architecture (NoC, DRAM, Cache, MMU)
- Understanding of how to leverage performance modeling to support architectural exploration, with exposure to heterogeneous hardware architectures
- Understanding of HW power, performance and area trade offs
- Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
Nice To Haves
- Experience working and communicating cross functionally in a team environment
- Intent to return to degree-program after the completion of the internship/co-op
- Experience in academic computer architecture simulators such as GEM5, SIMICS, etc
- Publication track record in computer architecture conferences is a plus - covering areas in high performance computing, memory systems, multi-core and/or accelerator architectures (e.g., ISCA, ASPLOS, MICRO, HPCA, DAC, NOCS, ISPASS, PACT, etc.)
Responsibilities
- Build APIs and/or custom wrappers to integrate various perf modeling components, develop test suites to formally verify the functionality and performance of the integrated models
- Identify areas of optimization to increase the speed of simulation infrastructure either through code refactoring or code restructuring
- Conduct performance & power explorations of various architectural components using built performance models (including blocks such as NoC, DRAM, MMUs, etc)
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What This Job Offers
Career Level
Intern
Industry
Broadcasting and Content Providers
Education Level
Ph.D. or professional degree
Number of Employees
5,001-10,000 employees
