Reliability Principal Engineer

Skywater•Bloomington, MN

About The Position

SkyWater is hiring a highly skilled Reliability Principal Engineer with a deep understanding of Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) CMOS technology. As a Reliability Engineer in our organization, you will be responsible for ensuring the robustness, durability, and long-term performance of our semiconductor products. Your expertise in FEOL and BEOL CMOS technology will play a pivotal role in optimizing the reliability of our technology.

Requirements

10+ years experience with BS, 7-10 years of experience with MS, 5+ years of experience with PhD in Electrical Engineering, Physics, Materials Science or a related field.
Demonstrated semiconductor reliability experience (or equivalent), with demonstrated technical leadership across FEOL and BEOL reliability.
Deep expertise in reliability physics, accelerated testing, statistical analysis, and lifetime modeling, demonstrated ability to establish qualification strategies and POR requirements.
Hands-on familiarity with reliability test instrumentation and workflows (wafer-level reliability, parametric characterization, stress systems) and with failure analysis methodologies.
Proficiency in statistical analysis software like JMP, Minitab, R, or Python for data analysis, data visualization, and reliability data modeling.
Experience with reliability simulation tools, such as RelXpert for modeling and simulating reliability aspects of semiconductor devices and circuits.
Familiarity with semiconductor design and simulation tools like Cadence Virtuoso, Synopsys HSPICE, or TCAD simulation tools for verifying the reliability of integrated circuits at the design stage.
Proven cross-functional collaboration and strong written and verbal communication skills, including customer-facing technical discussions.
US Citizenship Required: This position will require the holding of, or ability to obtain, a US government security clearance.

Responsibilities

Set and own the reliability strategy, standards, and qualification roadmaps across assigned technology nodes and product families, define and maintain the reliability POR including stress conditions, sample plans, success criteria, and reporting requirements.
Architect and lead end-to-end reliability characterization and qualification spanning wafer, package, and product-level testing, ensure efficient coverage of operating corners, environmental conditions, and application-driven stress profiles.
Own FEOL reliability assessment and mitigation, including: BTI (NBTI/PBTI), HCI, TDDB, charge trapping and interface-state generation, oxide integrity, and related device wear-out mechanisms, translate findings into process/ design recommendations and operating limits.
Own BEOL reliability assessment and mitigation, including: electromigration (EM), stress migration (SM), dielectric integrity, corrosion/contamination-related risks as applicable, and interconnect/via/TSV-related reliability where relevant, translate findings into layout/process guidance and reliability limits.
Develop, validate, and govern lifetime projection methodologies (e.g., Weibull statistics, acceleration models, temperature/field dependencies), clearly document assumptions, confidence, and limitations for decision-making.
Lead advanced failure analysis and root-cause investigations, establish hypotheses, design targeted experiments/DOEs, and drive cross-functional corrective and preventive actions to closure.
Represent reliability in executive program reviews and customer engagements, communicate technical risk, confidence level, and required actions in clear, decision-oriented language.
Drive organizational capability improvements: mentor senior engineers, standardize test/analysis workflows, champion automation and data quality, and influence lab/tool investments to close capability gaps.

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