About The Position

This opening work on chip design which enables 10Gbps/40Gbps/100Gbps/400Gbps backplane/cable/optical fiber communication architect block level design specifications from the marketing requirements and/or system requirements prepare detailed design document, timing constraint file HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL/gate level simulations & silicon debugging scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc. prepare block level resource requirements & development schedule generate verification & test plans for design validation Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc. silicon bring up

Requirements

  • B.S degree in EE or computer Engineering. Minimum of 12 years of work experience with direct related technical skill
  • M.S degree/Ph.D in EE or Computer Engineering with 10 years of work experience.
  • Good knowledge of ARM subsystem
  • Good knowledge of high speed digital circuit design.
  • Good knowledge of 10G/100G Ethernet and OTN network
  • Strong analytical and problem solving skills as well as hands-on lab debugging experiences
  • Good knowledge of RTL simulation and synthesis.
  • In-depth knowledge for design for low power and design for test and design for manufacturing.
  • Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or Python, and C.
  • Self-motivated, excellent communication skills and ability to excel in a team environment.
  • Good organization skills, able to follow through & bring issue to closure
  • Understand the entire IC development flow & procedure including silicon volume production qualification requirements & procedures
  • Enthusiastic & enjoy IC development works
  • Be able to work with teams at remote locations with different time zone.

Nice To Haves

  • Good knowledge of digital signal processing and error correction code is a plus
  • Experience with High-level Synthesis in design and verification is a plus.
  • DSP design knowledge is a plus
  • Knowledge Backplane/cable/optical fiber communication is a plus

Responsibilities

  • architect block level design specifications from the marketing requirements and/or system requirements
  • prepare detailed design document, timing constraint file
  • HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL/gate level simulations & silicon debugging
  • scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc.
  • prepare block level resource requirements & development schedule
  • generate verification & test plans for design validation
  • Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc.
  • silicon bring up

Benefits

  • This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
  • Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.
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