R&D Engineer IC Design 4
About The Position
You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow. · Ability to work independently as well as part of a large team spanning multiple geographies.
Requirements
- BS/MS in Electrical or Computer Engineering or equivalent
- Requires 6+ years with MS or 8+ years with BS in ASIC design / implementation
- Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.
- Requires proficiency with the following design tools / flows:
- TCL/Perl scripting
- Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler
- Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries
- Understanding of liberty LIB models for timing
- Formal verification (Synopsys Formality / Cadence Conformal)
- Spyglass Lint
- Power analysis of RTL and gate level netlists
- Familiarity with DFT (design for test) and scan methodology
- Version control (svn, git, etc)
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
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What This Job Offers
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
