You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow. · Ability to work independently as well as part of a large team spanning multiple geographies.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees