PTPX/Power Estimation and EMIR Engineer

Quest Global
3d$150,000 - $190,000Onsite

About The Position

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries. We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

Requirements

  • Needs to have deep PTPX Power-estimation expertise and strong EMIR experience.
  • The work is to run PTPX simulations on multiple blocks, ensure that the simulations are correct, analyze PTPX data and work with block owners in reducing power.
  • So this Engineer must have very strong Power Estimation Experience
  • Must have solid PD knowledge to run through EMIR for doing EMIR Analysis.

Responsibilities

  • Develops and drives Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs.
  • Actively works on power analysis, power optimization, simulation and roll-ups using Synopsys PTPX and RTLA.
  • Collaborating with the Various SoC and IP teams on various power projections and requirements, including silicon power capture and correlation with pre-si estimates.
  • Performed data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation.
  • Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction.

Benefits

  • health insurance
  • paid time off
  • retirement plan
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