Programmable Logic and ASIC Design Center of Excellence Lead

Lockheed Martin•Orlando, FL

2d•Hybrid

About The Position

You will be the Programmable Logic & ASIC Center of Excellence (CoE) Lead for the Missiles & Fire Control (MFC) organization. Our CoE provides end to end hardware development for programmable logic devices, custom ASICs and system on chip solutions, delivering unified, reusable flows and metrics that support multiple MFC programs. What You Will Be Doing As the PL/ASIC CoE Lead you will set the strategic and technical direction for PL and ASIC development, define the CoE charter and roadmap, align scope with senior leadership, and own tool/flow automation and continuous integration gates. You will drive common core digital and verification standards, ensure consistency across tools and processes, and mentor talent while contributing expertise to MFC programs.

Requirements

MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance.
Bachelor’s degree in Electrical Engineering or related field; Master’s degree preferred.
Minimum 20 years of hands‑on PL and/or ASIC design, analysis, verification, and qualification across defense‑grade programs.
At least 5 years of experience within Lockheed Martin, specifically in the Missile & Fire Control (MFC) business area, with a history of high performance.
Demonstrated success leading a CoE or comparable cross‑functional technical group.
Deep knowledge of LM MFC PL and/or ASIC design tools and process.
Proven record of building training programs or apprenticeship tracks for electrical engineers.
Excellent written and verbal communication.

Nice To Haves

Current or emeritus Group Technical Staff (GTS) member or Lockheed Martin Fellow, demonstrating recognized technical leadership within LM.
Active participation in internal technical focus groups or communities of practice.
Exposure to AI‑assisted layout tools, generative design, or model‑based systems engineering (MBSE) applied to PL and/or ASIC design.
Proficiency with HDL languages (SystemVerilog or VHDL) and UVM‑based verification.
Experience with common‑core digital standards: architecture, micro‑architecture, clocking/reset strategies, and coding/verification templates.
Familiarity with continuous integration (CI) pipelines, build/release flow ownership, and versioning for tools such as Vivado or Quartus.
Knowledge of emulation/acceleration platforms (e.g., Synopsys ZeBu, Cadence Palladium) and formal verification techniques.
Understanding of PLD implementation details: device constraints (XDC/SDC), timing closure, board‑level bring‑up, and hardware‑in‑the‑loop testing.
Experience with ASIC physical design, sign‑off (STA, SI, DRC, LVS), design‑for‑test (scan, JTAG, ATPG, MBIST), and low‑power design strategies.
Ability to develop and deliver curriculum, apprenticeship programs, and technical training for engineers.
Strong stakeholder management and communication skills with senior leadership.

Responsibilities

Defining, maintaining and regularly updating the CoE charter, roadmap and multi year improvement plan.
Chairing CoE meetings, hosting quarterly steering committee reviews and aligning CoE deliverables with VP level goals, funding streams and departmental initiatives (e.g., common architecture, design reuse, tool modernization).
Acting as the single point of authority for PL/ASIC design tools (Vivado, Quartus, Synopsys, Mentor), scripts and automation workflows; leading continuous improvement of design automation (DA) flows and engineering process metrics.
Establishing and enforcing common digital design and verification standards (RTL coding, UVM, DFT, low power methodologies) across MFC programs.
Overseeing PLD and ASIC implementation activities, including architecture definition, RTL development, functional verification, timing closure, physical design, design for test (DFT), low power strategies and tape out readiness.
Managing post silicon bring up, validation and debug activities, and ensuring successful transition from silicon to system integration.
Driving creation of reusable assets (templates, checklists, reference designs) and coordinating IRAD projects that advance PL/ASIC reuse and emerging technologies.
Designing, delivering and certifying CoE training curriculum, apprenticeship programs and technical workshops; mentoring junior engineers and championing career path development.
Consolidating and disseminating CoE communications to staff and senior stakeholders; maintaining configuration control and documentation in LM PLM tools.
Liaising with senior leadership (VP, Director, Section Managers) to secure resources, drive cross program adoption and support interview panels and recruitment.
Contributing technical expertise to MFC programs as an individual contributor on select projects (part time CoE role).