Siemens Corporation-posted 29 days ago
Full-time • Mid Level
Onsite • Wilsonville, OR
5,001-10,000 employees
Computer and Electronic Product Manufacturing

Work collaboratively with Tessent R&D to prototype, evaluate, and test new DFT products and features within complex IC design flows. Work with customers as well as business stakeholders such as regional application engineers, global support engineers, and marketing. Lead beta programs and support beta partners. Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes. Develop and review tool documentation such as User and Reference manuals. Develop new flows to integrate and test new Tessent technologies. Create test cases with Tessent and some 3rd party tools to replicate customer issues. Explain complex principles in simple terms to broad audiences. Review customer and AE questions, discussing steps to resolution internally. Propose support responses, with feedback from senior engineers. Attend internal meetings to learn the process for PE role.

  • Work collaboratively with Tessent R&D to prototype, evaluate, and test new DFT products and features within complex IC design flows.
  • Work with customers as well as business stakeholders such as regional application engineers, global support engineers, and marketing.
  • Lead beta programs and support beta partners.
  • Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes.
  • Develop and review tool documentation such as User and Reference manuals.
  • Develop new flows to integrate and test new Tessent technologies.
  • Create test cases with Tessent and some 3rd party tools to replicate customer issues.
  • Explain complex principles in simple terms to broad audiences.
  • Review customer and AE questions, discussing steps to resolution internally.
  • Propose support responses, with feedback from senior engineers.
  • Attend internal meetings to learn the process for PE role.
  • Employer will accept a Bachelor's degree, or foreign equivalent, in Electrical Engineering, Computer Engineering or related field and 24 months of experience in the job offered or in a Product Engineer-related occupation. Alternatively, employer will accept a Master's degree, or foreign equivalent, in Electrical Engineering, Computer Engineering or related field and no experience.
  • Experience in DFT for ASICs and SOCs including Automatic test pattern generation (ATPG), Internal scan & embedded scan compression (EDT), and Memory built-in self-test (MBIST) and repair (BISR).
  • Experience with Advanced DFT implementation technologies including Packetized test delivery (SSN), On-chip Clock Control (OCC), and hierarchical DFT implementation.
  • Experience with chip front-end design disciplines including RTL coding and verification using Verilog/SystemVerilog and Simulation.
  • Experience with chip back-end design disciplines Synthesis, Static Timing Analysis, Simulation and debugging Scan, ATPG, and DRCs, and ATPG Coverage analysis and improvement.
  • Creating design flows and testcases to replicate behaviors or to setup new features.
  • Experience with Tessent products including Tessent Streaming Scan Network, Tessent TestKompress, Tessent ScanPro, Tessent IJTAG, Tessent MemoryBIST, and Tessent Shell.
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