Product Development Engineer

Altera•San Jose, CA

About The Position

About Altera For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries. Join us in our journey to becoming the #1 FPGA company! About the Role Our Product Development Team is responsible for performing silicon failure and yield analysis to optimize RISO and PRQ goals. We support wafer yield ramp and fab process optimization in early production stage for wafer Sort and Class yield thru systematic test data analysis to isolate and mitigate defects and failures. We are seeking motivated Product Development Engineer to help us in following areas but not limited to it. Drives and develops testability and manufacturability of integrated circuits from the component debug feasibility stage through production ramp. Contributes to performing Yield Analysis to identify yield limiting issues using Data Science, Data Analytics and Machine Learning techniques to isolate failures faster. Interfaces with fabrication, sort, assembly, component debug, test program developers, failure analysis, quality and reliability, and manufacturing groups to enable healthy silicon and on-time PRQ. Identify root cause of systematic yield issues by applying test program/pattern skills and propose mitigation plan in defined timeline leading to PRQ. Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis. Maintain up-to-date Yield Dashboard & KPI to identify yield issues and communicate to stake holders and mgmt. Develop new yield modelling methods and AI algorithms using machine learning to deliver world class yield predictability. Advance knowledge and understanding of FPGA architecture/design, fab process, test program/content, sort and class defects and its root causes to apply in solving problems faster. Develops and debugs complex test programs/test patterns to convert design validation vectors and resolve silicon level yield limiters. Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp.

Requirements

Bachelor’s degree in Electrical Engineering or a related field
7+ years of industry experience in Yield Engineering, Test Engineering, or Silicon Manufacturing Engineering for advanced semiconductor products.

Nice To Haves

Master’s degree or PhD in Electrical Engineering or a related field.
5+ years of industry experience in Yield Engineering, Test Engineering, or Silicon Manufacturing Engineering for advanced semiconductor products.

Responsibilities

Drives and develops testability and manufacturability of integrated circuits from the component debug feasibility stage through production ramp.
Contributes to performing Yield Analysis to identify yield limiting issues using Data Science, Data Analytics and Machine Learning techniques to isolate failures faster.
Interfaces with fabrication, sort, assembly, component debug, test program developers, failure analysis, quality and reliability, and manufacturing groups to enable healthy silicon and on-time PRQ.
Identify root cause of systematic yield issues by applying test program/pattern skills and propose mitigation plan in defined timeline leading to PRQ.
Performs ATE device characterization, utilizes that data to define datasheet specifications and performs yield analysis.
Maintain up-to-date Yield Dashboard & KPI to identify yield issues and communicate to stake holders and mgmt.
Develop new yield modelling methods and AI algorithms using machine learning to deliver world class yield predictability.
Advance knowledge and understanding of FPGA architecture/design, fab process, test program/content, sort and class defects and its root causes to apply in solving problems faster.
Develops and debugs complex test programs/test patterns to convert design validation vectors and resolve silicon level yield limiters.
Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp.