Product Development Engineer

Advanced Micro Devices, Inc•Austin, TX

1d•Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Join a global product reliability team that drives product qualifications for new CPU, APU, GPU, Adaptive SoCs and FPGA. This position is a highly visible role within the AMD engineering Design for Reliability team, responsible for defining and implementing reliability methodologies, developing predictive models, and influencing design practices to ensure robust product performance across operating voltages, temperatures, and process window. The engineer will possess technical authority in a fast paced, dynamic environment that requires decision making at strategic and tactical levels. THE PERSON: The position provides influence that mandates strong analytical and technical skills. Demonstrated success working in Design for Reliability Engineering, with strong familiarity in analog, mixed-signal, and SoC semiconductor reliability.

Requirements

The position provides influence that mandates strong analytical and technical skills.
Demonstrated success working in Design for Reliability Engineering, with strong familiarity in analog, mixed-signal, and SoC semiconductor reliability.
Experience in semiconductor reliability and design engineering, with a focus on analog/mixed-signal or SoC devices.
Strong proficiency in statistical reliability analysis tools, JMP, MATLAB, or Python-based modeling frameworks.
Experience in stress modeling, lifetime extrapolation, and acceleration modeling for EM/TDDB/BTI, semiconductor degradation mechanisms methodology.
Knowledge of reliability characterization, qualification methods, and failure analysis workflows.
Demonstrated ability to correlate pre-silicon predictions with post-silicon data and tune modeling assumptions accordingly.
Familiarity with semiconductor process technologies, transistor-level simulations, and device physics fundamentals.
Strong data interpretation skills and ability to communicate complex datasets clearly across functional boundaries.
BS/MS or PhD in Electrical Engineering, Physics, Materials Science or equivalent.

Nice To Haves

Understanding of Silicon Photonics reliability, test and manufacturing methods, a plus.
Understanding of advanced silicon and 3D-stacked/CoWoS packaging reliability, a plus.
Understanding of Silicon Failure Analysis methods and interpreting FA results, a plus.
Understanding of Soft Error Rate (SER), Single Event Latch-up (SEL) assessment methods, a plus.
Additional coursework or certification in reliability engineering, statistical modeling, or design-for-reliability (DFR), plus.

Responsibilities

This role spans the full reliability development cycle, from pre-silicon design assessments and physics-based modeling through post-silicon validation and lifetime performance analysis.
Lead pre-silicon reliability analysis for analog, mixed-signal, and SoC circuits, focusing on mechanisms such EM, TDDB, HCI, BTI, ESD, and parametric shifts.
Develop physics-of-failure-based lifetime and reliability models (Weibull, lognormal, exponential) that derive key reliability metrics including FIT, DPPM, AFR.
Lead cross-disciplinary reviews with design, process, and reliability, to solve reliability constraints through technical insight, data analysis.
Collaborate with design teams to implement design-for-reliability (DFR) guidelines and aging-aware simulation methodologies.
Leverage models to establish design constraints and lifetime projections.
Collaborate with post-silicon reliability teams to characterize products through Wafer Level Stress, Burn-In, HTOL, device parametric guardband, and post-silicon screening strategies.
Drive understanding of Intrinsic and Extrinsic Silicon reliability mechanisms, Design-Process interactions, and acceleration models.
Correlate pre-silicon modeling outputs with post-silicon measurements to refine lifetime projections and improve predictive accuracy.
Enhance internal reliability modeling infrastructure to automate data collection, lifetime prediction, and statistical reliability analysis.
Communicate across design, technology, test, and product teams to influence system-level reliability performance.