Processor ASIC RTL Design Engineer

Qualcomm • San Diego, CA

8d

About The Position

A variety of high performance, low power Hexagon/NPU cores are at the heart of Qualcomm’s multi-tier mobile SOC, Server IoT, Automotive roadmap. The Hexagon architecture is designed to deliver performance with low power and area over a variety of applications like Audio, Modem, AI, IoT and Automotive.
This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor design and integration is a definite advantage.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 1+ year of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field.
• 2+ years of experience with high-performance microprocessor design.

Nice To Haves

• 2+ years of practical experience with details of RTL development including: functional and structural RTL design in system Verilog, design partitioning, simulation and regression, collaboration with design verification team. Familiar with latest design tools (such as linting, CDC, LEC, CLP etc)
• Experience with the following disciplines is highly desirable: Processor integration
• Bus interface
• Computer architecture

Responsibilities

• Work with system architecture team to define micro-architecture documentation for various blocks in Hexagon/NPU and sub-system
• Develop RTL for multiple logic blocks of Hexagon/NPU and sub-system for SoC integration
• Run various frontend tools to check for linting, clock domain crossing, power intent etc
• Work with physical design team on design constraints and timing closure
• Work on area and power optimization
• Work with verification team to collaborate on test plan, test debug, coverage plan and coverage closure
• Support internal hardware integration
• Provide ideas and further the innovation of ASICs, IP cores, and process flows

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees