Principal VLSI Design Engineer, Sunnyvale, CA

Hewlett Packard Enterprise • Sunnyvale, CA

1d • Onsite

About The Position

Principal VLSI / ASIC Design Engineer (Networking ASICs) Role Summary You will architect, design, and implement complex networking ASICs. You will create chip‑level and block‑level architecture and micro‑architecture, write high‑quality RTL, and work closely with verification and physical design teams to deliver clean, efficient, and high‑performance silicon. US Citizenship preferred Location: Sunnyvale, CA Onsite work required weekly 2 days per week; Tuesdays and Thursdays

Requirements

• Strong understanding of ASIC architecture and micro‑architecture.
• Strong background in networking ASICs (switching, routing, packet processing, or similar preferred).
• Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage
• Strong knowledge of digital design fundamentals, pipelining, clocking, resets, FIFOs, arbiters, and data path design.
• Experience working with verification teams and understanding of UVM‑based flows.
• Experience working with physical design teams and understanding constraints for timing, power, and area.
• Familiarity with EDA tools for simulation, synthesis, lint, CDC, timing analysis, and power analysis.
• Good written and verbal communication skills.
• History of technical contributions, innovation, or mentorship.
• Bachelor’s, Degree in Computer Science, Master’s, or PhD in Electrical Engineering, Computer Engineering, or similar.

Responsibilities

• Define ASIC architecture for networking chips, including data paths, packet processing, control logic, memory structures, and interfaces.
• Develop detailed micro‑architecture for complex blocks and ensure they meet functional and performance goals.
• Write clear, efficient, synthesizable RTL (SystemVerilog/Verilog) for the designed blocks.
• Create assertions and assist in functional coverage
• Work closely with verification engineers to ensure the RTL is fully tested, bug‑free, and meets all functional requirements.
• Provide guidance to the verification team on test plans, coverage goals, corner cases, and expected behavior.
• Collaborate with physical design engineers to ensure the design meets timing, area, and power targets.
• Review synthesis, timing, and power reports, and update RTL or micro‑architecture as needed.
• Participate in design reviews, provide clear feedback, and ensure compliance with design guidelines.
• Support integration and debug during simulation, emulation and silicon bring‑up.
• Identify technical risks early and propose simple, effective solutions.

Benefits

• Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level