Principal Systems Design Engineer, HBM

Micron Technology • Folsom, CA

69d • $165,000 - $280,000

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The position involves responsibilities such as floorplanning the full chip level, design partitioning, top level synthesis with multiple hard macro IP blocks, developing automated high-speed matching routing, performing verification like LVS/DRC/Antenna, quality checks, and supporting documentation. The role requires timely delivery of block-level layouts with acceptable quality and demonstrates leadership skills in planning, area/time estimation, scheduling, and execution to meet project schedules. The candidate will also guide junior team members in their execution of sub block-level layouts and contribute to effective project management while effectively communicating with global engineering teams.

Requirements

• 10+ years' experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Significant experience with industry APR tools like Innovis or Fusion Compiler.
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.).
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand design constraints and implement high-quality layouts.
• Ability to understand design hierarchy and different architectures for Memory designs.
• Excellent problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.

Responsibilities

• Responsible for floorplanning the full chip level.
• Responsible for design partitioning.
• Responsible for top level synthesis with multiple hard macro IP blocks.
• Responsible for developing automated high-speed matching routing.
• Perform verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for timely delivery of block-level layouts with acceptable quality.
• Demonstrate leadership skills in planning, area/time estimation, scheduling, and execution to meet project schedule/achievements in multiple project environment.
• Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Benefits

• Choice of medical, dental and vision plans.
• Benefit programs that help protect your income if you are unable to work due to illness or injury.
• Paid family leave.
• Robust paid time-off program.
• Paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees