Principal System Validation Engineer – SerDes/Ethernet (PAM4)

Astera LabsSan Jose, CA
1d$209,000 - $230,000

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.

Requirements

  • Strong academic and technical background in electrical or computer engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
  • 8-12 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

Nice To Haves

  • Strong knowledge in scripting for automation of validation efforts (e.g. Python, Matlab)
  • Experience with silicon bring-up, debugging complex electrical and system performance issues, production ramp.
  • Very knowledgeable about common high-speed SerDes protocols like Ethernet, PCIe etc., and the electrical, system level specifications defined in the standard documents (IEEE802.3, PCIe Base Specification etc.)
  • Very knowledgeable about SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget.
  • Experience working with lab equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes and VNA
  • Experience with PAM4 SerDes validation (200G/100G/50G)
  • Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
  • Knowledge of Signal Integrity simulation tools
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude.
  • Think and act with the customer in mind!

Responsibilities

  • Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms.
  • Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion
  • Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions.
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service