Principal System Signal Integrity Engineer

ARM • Austin, TX

82d • $241,100 - $326,100 • Hybrid

About The Position

Arm is seeking a highly skilled Senior Signal Integrity Engineer to lead the development and optimization of high-speed signaling solutions across blades and racks within our advanced compute platforms. This role offers a unique opportunity to work at the intersection of silicon, interconnect, and system design! This position is based in Austin or San Jose and could potentially be performed onsite or remotely within the US. Join us today!

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of experience in signal integrity engineering for high-speed systems.
• Deep knowledge of high-speed signaling standards (e.g., PCIe Gen4/5/6, CXL, Ethernet up to 112G, DDR4/5).
• Strong expertise in simulation tools (e.g., HFSS, CST, ADS, Sigrity, SPICE) and lab instrumentation.
• Experience working with silicon teams and system designers to optimize I/O and channel performance.
• Experience collaborating with interconnect vendors and ODMs on hardware design and qualification.
• Excellent communication and multi-functional teamwork skills.

Nice To Haves

• Experience in hyperscale or data center hardware environments.
• Knowledge of thermal and mechanical considerations in SI design.
• Experience with scripting languages (e.g., Python, MATLAB) for simulation automation and data analysis.

Responsibilities

• Lead signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces (e.g., PCIe, SerDes, CXL, DDR, Ethernet) across blade and rack-level system architectures.
• Work closely with Arm silicon teams to define I/O requirements and optimize signal paths across chip to chip and chip to end devices.
• Collaborate with connector and cable vendors to evaluate and select interconnect solutions that meet system performance targets.
• Engage with Original Design Manufacturers (ODMs) to guide board and system layout for optimal signal and power integrity.
• Perform time-domain and frequency-domain simulations using tools like Ansys HFSS, Keysight ADS, Cadence Sigrity, or similar.
• Drive the development of SI/PI design guidelines, stack-ups, and routing rules for system and board-level design.
• Support lab validation for SI/PI performance using VNA, TDR, BERT, and high-speed oscilloscopes.
• Review and approve schematics, layout, and simulation reports for blade, backplane, and rack-level hardware.

Benefits

• Competitive salary range of $241,100-$326,100 per year.
• Total reward package shared during recruitment process.
• Accommodations available during recruitment process.
• Hybrid working environment that supports high performance and personal wellbeing.
• Commitment to equal opportunities and a diverse workplace.

What This Job Offers

• Career Level: Senior
• Education Level: Bachelor's degree