Principal Static Timing Analysis (STA) Engineer – SoC Design

Marvell Technology • Westborough, MA

11d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The DCE team at Marvell is seeking a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes. Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites. If you're looking to apply your STA expertise in a dynamic and forward-thinking environment, this could be a great opportunity to explore.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree
• Proven success in timing analysis and closure across multiple ASICs/SoCs
• Experience with advanced timing concepts: SI, CDC, LVF, POCV, etc.
• Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX environments
• Strong communication skills and ability to work independently and collaboratively

Nice To Haves

• Experience leading timing closure efforts across teams preferred
• Familiarity with timing methodology and flow development preferred

Responsibilities

• Lead timing closure for sub-system/partition or full-chip level designs
• Collaborate with RTL, DFT, and IP teams to drive iterative timing feedback and closure
• Deliver timing collateral and signoff reports per project milestones
• Perform timing correlation between PD tools and signoff tools; support early feasibility studies
• Generate and push down ECOs to block-level teams
• Mentor junior engineers and provide technical leadership across teams
• Develop automation scripts in Perl, Python, and TCL to improve timing workflows
• Manage timing constraints compatible with synthesis, P&R, and STA tools

Benefits

• Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees