Principal Software Engineer - Low Power Verification

Cadence-posted about 1 month ago
Full-time • Senior
San Jose, CA
5,001-10,000 employees
Ambulatory Health Care Services
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We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows.

  • Develop and optimize low-power verification software for Palladium and Protium platforms.
  • Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows).
  • Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
  • Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows: AVIP + UPF + 2/4-state UVMA + UPF + 2/4-state MC + UPF Dielets + UPF
  • Consolidate UPF software across Palladium and Protium platforms.
  • Support key initiatives such as: MC+PPC flow with UPF 4-state Compilation time optimization for UPF Full Vision UPF probe integration SAGE UPF debug with Verisium
  • Strong proficiency in object-oriented design and C++ programming.
  • Experience with standard C/C++ libraries and the C++ Standard Template Library (STL).
  • Proven ability to develop high-performance software for large-scale data processing.
  • Scripting experience in Perl, Tcl/Tk, and/or Python.
  • Familiarity with IEEE 1801 standards and UPF implementation.
  • Experience with Verilog, SystemVerilog, and VHDL.
  • paid vacation and paid holidays
  • 401(k) plan with employer match
  • employee stock purchase plan
  • a variety of medical, dental and vision plan options
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