Acara Solutions has been providing advanced manufacturing and technology firms our staffing related services since the 1950's. Our San Diego (or San Jose) low power wireless technology client is looking for a Principal SoC Full-Chip Physical Design Implementation & Verification Engineer to join their organization as a direct salaried employee. The base salary target is $220K with possible flexibility up to $240K. The key qualifications for this principal physical design engineer covers: Full chip floor planning, bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification. The entire SOC implementation and verification flow from RTL-to-GDS that includes full chip floor plan, place and route, CTS, and layout verification sign off on lower power SoC. This is the full SoC physical design flow, and it's central to what many principal-level SoC engineers are responsible for managing or guiding. We are seeking a highly experienced and innovative engineer to lead the full-chip implementation and verification of complex System-on-Chip (SoC) designs. This role involves overseeing the end-to-end process from RTL development through to post-silicon validation, ensuring the delivery of high-performance, reliable, and power-efficient SoCs.