Principal Silicon Validation Engineer

Astera Labs•San Jose, CA

About The Position

The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product’s parametric compliance. Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs.

Requirements

Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
Proven track record solving problems independently, preferably as a tech lead
Experience working on debug and bring-up of complicated SoC’s with high-speed interfaces such as PCIe/802.3 Ethernet
Strong problem-solving skills, ability to solve problems independently
Basic knowledge of key, high-speed design blocks such as PLL’s, CTLE, DFE, Tx EQ, PAM4 signaling
Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Nice To Haves

Experience in system testing, characterization, margin analysis and optimization of high-speed, multi-gigabit data links over long and short channels
Familiarity with PCIe or Ethernet especially Electrical Compliance sections
Hands-on experience with signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces
Working knowledge of C or C++ for embedded FW
Familiarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signaling
Working knowledge of common serial data specifications such as I2C, SPI, etc
Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues