Principal RFIC/PLL Design Engineer

BLUE ORIGIN • Spokane, WA

2d • Onsite

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! - We are seeking a Principal PLL Design Engineer to lead the development of Phase-Locked Loops (PLLs) in advanced CMOS/SiGe processes. This role requires extensive design experience, particularly at mmWave frequencies, and is essential for advancing our technology offerings in space communication systems. You will be responsible for delivering state-of-the-art performance while contributing to innovative solutions that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Requirements

• MS or PhD in Electrical Engineering or a related technical discipline.
• 10+ years of experience in the design and development of high-speed (>20GHz) PLLs and LOGEN for high-performance applications at RF and mmWave frequencies.
• Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
• Extensive experience in PLL silicon characterization and debugging.
• Strong background in fundamental analog/RF building blocks, including amplifiers, filters, and mixers.
• Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Nice To Haves

• Strong expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.
• Extensive experience with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers.
• Fundamental understanding of device physics for process selection and performance optimization.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Responsibilities

• Lead the design, development and integration of PLLs in advanced CMOS and SiGe technologies, focusing on performance optimization and trade-off analysis.
• Utilize full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborate with RF system architects to define requirements for PLLs and their sub-blocks based on system specifications, ensuring seamless integration into RF payloads and terminals.
• Oversee layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.
• Work closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.
• Investigate and implement fundamental analog building blocks to enhance overall circuit performance and mentor junior engineers for best design practices in analog domain.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion.
• Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree