Principal Physical Design Engineer

Marvell Technology • Santa Clara, CA

81d • $146,850 - $220,000

About The Position

As a core member of Marvell's Central Physical Design team, you’ll provide backend design services to Marvell's SoC groups, working across a variety of complex designs that underpin data center, server, and networking applications. This team is dedicated to achieving high-performance and low-power goals for Marvell’s optical DSP and networking solutions, supporting multiple business models and targeted at the forefront of data infrastructure. As a Principal Physical Design Engineer specializing in chip-level Place and Route (PNR), you will play a pivotal role in defining Marvell’s physical design process and flow, ensuring successful delivery of high-performance designs in advanced technology nodes. Leveraging your expertise, you’ll directly influence the quality of Marvell’s next-generation products, guiding backend implementation from concept to tapeout and providing technical leadership on challenging SoC projects.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• 10+ years of hands-on experience in physical design and verification, with proven success in chip-level PNR and tape-outs of complex SoC designs.
• Demonstrated ability to lead chip-level backend implementation and deliver on schedule.
• Familiar with hierarchical design strategies and deep sub-micron technology (e.g., N7/N5), with knowledge of current design technologies used in major foundries.
• Extensive experience with timing analysis (Tempus, PrimeTime) and EM/IR-Drop/crosstalk analysis tools (Voltus, Celtic, PTSI, AstroRail).
• Skilled in physical verification tools and logic equivalence tools (LEC, Formality, Calibre) and extraction tools (QRC, StarRC).
• Advanced scripting abilities, especially in Makefile, Tcl, and Perl, with a focus on improving backend process efficiency.

Nice To Haves

• Detail-oriented, self-motivated, and an effective communicator, with a collaborative team-oriented approach.
• Planning and resourcing physical design work, cross functional collaboration.

Responsibilities

• Lead chip-level PNR activities, from floor planning and power grid design to clock tree synthesis, routing, and timing closure.
• Perform detailed timing, power and signal integrity signoff, including IR drop and crosstalk analysis, ensuring designs meet stringent performance and reliability targets.
• Manage physical verification tasks (DRC, LVS, antenna) to meet process and quality standards required for advanced semiconductor nodes.
• Act as a technical leader, guiding a team of physical design engineers on project-level backend implementation, and coordinate with frontend, integration, and verification teams.
• Develop and refine physical design methodologies and flows, collaborating cross-functionally to optimize design efficiency and alignment with project goals.
• Mentor and develop junior engineers, fostering an environment that encourages innovation and excellence.
• Use scripting skills to streamline and automate workflows (Makefile, Tcl, Perl), enhancing design efficiency across projects.
• Maintain a deep understanding of physical design tools, including Cadence Innovus, Synopsys IC Compiler, and Fusion Compiler, ensuring best practices in tool use and integration.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees