Principal Physical Design Engineer

Astera Labs•San Jose, CA

4h•Onsite

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. As an Astera Labs Principal Physical Design Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Requirements

Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
Strong scripting ability (Tcl, Python, Perl).
Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Nice To Haves

Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
Experience working with IP vendors for both RTL and hard-macro integration.
SystemVerilog/Verilog familiarity.

Responsibilities

Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.
Identify RTL issues early and work with frontend team on resolution.
Hands-on experience with various custom clocking techniques.
Experience with high-speed designs with serdes/ddr IPs.
Good understanding of PnR tool and signoff flows like Extraction, STA, Formality, EM-IR and DRC/LVS etc
Hands-on experience with ECO flow using PT DMSA and hyperscale models for bigger chips
A good understanding of SDC constraints, be able to interact with design team on constraints refinement.
Work with top level owners on defining and managing I/O timing budgets across hierarchical designs.
Knowledge of different ways to build hierarchical design (black-box model, ETM or abstract model etc).
Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.