Principal Mixed Signal Engineer, Texas Institute for Electronics

University of Texas at Austin•Austin, TX

2d•Hybrid

About The Position

Texas Institute for Electronics (TIE) is a transformative, well-funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative. Its mission is to advance the state of the art in 3D heterogeneous integration (3DHI), chiplet-based architectures, and multi-component microsystems, catalyzing breakthroughs across microelectronics, artificial intelligence, quantum computing, high-performance computing, and next-generation healthcare devices. Backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, TIE is building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing. TIE’s 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions to deliver unprecedented performance and energy efficiency, operating at the intersection of defense electronics and commercial markets. The purpose of the Principal Mixed Signals Engineer is to develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms. This includes defining architecture specifications, collaborating with teams to optimize performance, and engaging with semiconductor industry partners to shape ecosystem directions.

Requirements

M.S. in Electrical Engineering with emphasis on analog/mixed-signal or high-speed circuit design (or equivalent practical experience).
12+ years of experience in mixed-signal or high-speed I/O circuit design for SoC/ASIC, with direct involvement in SerDes, UCIe, or comparable die-to-die/chip-to-chip interface IP.
Deep expertise in high-speed transceiver design—including TX/RX front-ends, CDR, equalization (CTLE, DFE), PLLs/DLLs, and signal integrity analysis for multi-Gbps links.
Hands-on experience with silicon bring-up, lab characterization (high-speed oscilloscopes, BER testers, network analyzers), and production test development on ATE platforms.
Proficiency with industry-standard analog/mixed-signal EDA tools (Cadence Virtuoso/Spectre, Synopsys HSPICE, Ansys HFSS/SIwave) and parasitic-aware simulation methodologies.
Strong cross-disciplinary collaboration—able to interface with digital design, packaging, EDA, and process engineering teams to close mixed-signal performance across the 3DHI stack.
Proven record of taking high-speed mixed-signal IP from design through silicon validation and into production.

Nice To Haves

Ph.D. in Electrical Engineering with emphasis on analog/mixed-signal or high-speed circuit design (or equivalent practical experience).
Direct design experience with UCIe 2.5D (single-ended, shoreline-optimized) and/or UCIe 3.0D (hybrid-bonding, ultra-short-reach) physical-layer implementations.
Familiarity with heterogeneous (multi-material and/or multi-function) integration challenges—including crosstalk modeling, power delivery network design, and signal integrity in 2.5D/3D hybrid-bonding and interposer stacks.
Experience designing SerDes or high-speed I/O IP at 28 Gbps and above (e.g., 56G/112G PAM4), with end-to-end ownership spanning specification, design, tape-out, silicon characterization, and production test.
Knowledge of interconnect and chiplet standards (UCIe, BoW, CXL, PCIe Gen 5/6, NVLink, UALink) and their physical-layer requirements and compliance testing.
Track record of publications, patents, or industry leadership in mixed-signal circuit design, high-speed I/O, or SerDes architectures.

Responsibilities

Design and develop high-speed mixed-signal I/O circuits for UCIe 2.5D and 3.0D die-to-die interfaces in 2.5D/3D microsystems—enabling robust, low-latency chiplet interconnect across AI, HPC, and defense platforms.
Architect and optimize SerDes, clock/data recovery (CDR), equalization, and transceiver circuits for high-speed die-to-die and chip-to-chip links, including UCIe, PCIe physical layers.
Collaborate with packaging, EDA, and system modeling teams to co-optimize mixed-signal I/O performance across heterogeneous integration stacks—accounting for signal integrity, power delivery, crosstalk, and thermal effects unique to 3DHI.
Lead silicon bring-up, bench characterization, and production testing of high-speed I/O and mixed-signal circuits—developing test methodologies, ATE programs, and yield-improvement strategies from prototype through volume production.
Engage with industry partners and standards bodies (UCIe Consortium) to influence specification development and ensure TIE’s physical-layer implementations remain standards-aligned.
Mentor internal design teams on mixed-signal design methodologies, high-speed measurement techniques, and production test best practices for multi-die systems.
Translate mixed-signal design innovations into IP roadmaps and reference designs, driving alignment between research, productization, and customer enablement for UCIe-based chiplet ecosystems.

Benefits

Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
Voluntary Vision, Dental, Life, and Disability insurance options
Generous paid vacation, sick time, and holidays
Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
Flexible spending account options for medical and childcare expenses
Robust free training access through LinkedIn Learning plus professional conference opportunities
Tuition assistance
Expansive employee discount program including athletic tickets
Free access to UT Austin's libraries and museums with staff ID card
Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card