Principal Logic Design Engineer

Microsoft-posted about 1 year ago

$137,600 - $267,000/Yr

Full-time • Principal

Redmond, WA

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The Principal Logic Design Engineer will be a key member of Microsoft's Silicon team, focusing on the development of cutting-edge IP for various systems, including consumer products and cloud servers. This role requires a motivated self-starter who thrives in a technical environment, contributing to the design and implementation of microarchitecture, RTL design, and silicon validation while collaborating with various teams to achieve project goals.

Work with the architecture team to define and implement the microarchitecture of IP blocks.
Conduct RTL design, synthesis, static timing analysis, and silicon validation.
Interact with architects for feature definition and collaborate with various design teams.
Lead design verification and software teams throughout the program.
Ensure high-speed microarchitecture design and strong design team leadership.

9+ years of related technical engineering experience OR a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years of technical engineering experience OR a Master's degree in the same fields AND 4+ years of technical engineering experience OR a Doctorate degree in the same fields AND 3+ years of technical engineering experience.
Experience in Digital Design including microarchitecture specification development and RTL coding in Verilog/System Verilog.
Experience in developing/optimizing high-speed ASIC CMOS designs.
Proficiency in Verilog, System Verilog, and scripting languages such as Python, Ruby, or Perl.

15+ years of technical engineering experience.
Design knowledge of industry-standard bus interfaces such as AMBA AXI protocol.
Experience in basic floor planning, static timing analysis/closure, and working with physical design teams.
Experience in high-performance/power-efficient floating-point design.
Experience with ensuring chip design quality through design and checklist reviews.
Experience leading design teams in leading-edge technologies: 5 nm or newer.
Expertise in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and LINT closure.

Competitive salary range based on experience and location.
Potential eligibility for additional benefits and compensation.

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