Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-performance memory solutions for AI. In Micron's AI-optimized Memory Architecture organization, we partner closely with customers to design and deliver memory solutions purpose-built for emerging AI systems and applications. As a Principal Layout Designer in the AI-optimized Architecture team, you will drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads. Apply expert knowledge to deliver high-quality layout designs across analog, mixed-signal, and custom digital domains in collaboration with peer architecture, design, and packaging teams. Drive layout designs for early architecture concepts to demonstrate feasibility and identify optimizations. What you'll do Design and develop critical analog, mixed-signal, and custom digital blocks. Drive exploratory layout process for next-generation architectures, including floor planning, placement, and routing. Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. Collaborate and communicate across domains, including signal integrity, architecture, design, and advanced packaging, to ensure successful architecture exploration. What we're looking for: Minimum 6 years of experience with a Bachelor's or Master's in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience. Extensive hands-on layout experience with critical DRAM blocks and full designs. Experience with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS. Solid understanding of layout impacts: speed, capacitance, power, and area. Strong understanding of analog layout fundamentals: matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.
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Job Type
Full-time
Career Level
Principal