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As a Principal Layout Design Engineer at Qorvo, you will play a critical role in the layout of RF, analog, and mixed-signal integrated circuits for System on Chip (SoC) products that cater to automotive, industrial, and consumer applications. Your expertise will be essential in chip-level and block-level floor planning, where you will conceptualize and realize highly integrated RF, analog, and digital designs. You will be responsible for top-level and block-level layout designs, ensuring that all designs undergo rigorous circuit and layout verification checks, including LVS (Layout Versus Schematic), DRC (Design Rule Check), and ERC (Electrical Rule Check). In this position, you will engage in full analog layout design and optimize layout sizes for CMOS circuits, particularly in 40nm and smaller nodes. Collaboration is key, as you will interface with both analog and digital engineers located in the US and Europe, ensuring that all aspects of the design process are aligned and executed efficiently. Additionally, you will oversee the tape-out process, manage databases, and maintain thorough documentation and archiving practices to support the integrity and traceability of the design work.
