Principal Lab Validation Engineer

Astera Labs • San Jose, CA

117d • $203,000 - $230,000

About The Position

As an Astera Labs Principal Lab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions. You will directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. Collaborate with design, validation, and system engineering teams as needed. Modify device firmware to test out engineering theories leading to potential fixes or production screens. Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems. Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability. Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports. Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures. Develop and run stress tests and margining experiments to identify weak design or process corners. Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions). Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing. Document debug findings, propose design/process/test improvements, and contribute to FA methodologies. Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.

Requirements

• Minimum of a Bachelor’s in Electrical Engineering; Master’s degree preferred.
• Minimum of 10 years relevant experience, with 5 years’ hands-on mixed high-speed lab experience.
• Experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA.
• Python programming.
• Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity.
• Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing).
• Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures).
• Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity.
• Experience in post-silicon validation and bring-up of high-speed PHYs or retimers.
• Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures.
• Strong written and verbal communication skills.

Nice To Haves

• C (not C++).
• Experience with optics.
• Experience with chip-level security and RAS features.
• ATE (Automated Test Equipment) Advantest V93K.
• Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed.

Responsibilities

• Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions.
• Collaborate with design, validation, and system engineering teams as needed.
• Modify device firmware to test out engineering theories leading to potential fixes or production screens.
• Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems.
• Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability.
• Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports.
• Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.
• Develop and run stress tests and margining experiments to identify weak design or process corners.
• Provide feedback on system-level integration challenges for retimers and PCIe switches.
• Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing.
• Document debug findings, propose design/process/test improvements, and contribute to FA methodologies.
• Participate in new product development process to ensure readiness for customer returns before products are launched.
• Collaborate in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts.

Benefits

• Base salary range of $203,000 USD - $230,000 USD.
• In-person presence required, offering a unique opportunity to impact global operations directly.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 251-500 employees