Principal IPQA Automation Engineer

ARM•Austin, TX

27d

About The Position

Arm teams develop groundbreaking Silicon demonstrators which embeds the latest Arm Compute Sub-System IP (Intellectual Property) and other various outsourced IP. We are looking for a creative and hardworking principal engineer to join the IP Qualification team to verify these Third-Party IPs before they are embedded in SoC. Such TPIP are foundation IP (e.g. standard-cells, SRAM), NVM (e-fuse, anti-fuse), PLL, sensors, as well as sub-system Interfaces (controller + PHY) like LPDDR, USB, Ethernet or PCIe. You will join a newly formed team in Austin as well as collaborate with multiple other groups inside of Arm. For a Silicon demonstrator, you will lead the installation and the verification of all the TPIP EDA models to ensure they are in line with the Arm SoC design flow requirements, and they adhere to DFX (Design for Test, Debug, Reliability, Manufacturing and Yield) requirements as defined by Arm. For that, you will use the IP Qualification flow along with the EDA tools from major providers. You will analyze the deviations and share them with the SoC design teams for review and eventually report them to the IP providers for update. As a senior engineer, you will propose and lead the implementation of new checks to improve the coverage and to better ensure the compliance of the receivables with SoC flow and DFX.

Requirements

At least 18 years of post-master degree work experience in IP design or verification and/or implementation and signoff.
At least two of the following experiences are required:
Functional verification of IP blocks/subsystems.
RTL code Linting and CDC/RDC verification.
Scan stitching, ATPG and patterns simulation.
Synthesis, lowe-power (UPF) physical implementation and verification, timing and power signoff.
Power grid integrity (electro-migration, voltage-drop) and physical checks.
Scripting for tasks automation with Shells (e.g. Bash), TCL, Python or any other language.
Excellent interpersonal skills, strong initiative and open in engaging and learning various IP and the SoC reference design flow.

Nice To Haves

Experience in Verify-IP usage for Interface IP protocol verification.
Boundary scan integration (IEEE-1149).
SI/PI (signal/power integrity) checks at chip/package level.
Functional Safety and Cyber Security requirements.

Responsibilities

For a Silicon demonstrator, you will lead the installation and the verification of all the TPIP EDA models to ensure they are in line with the Arm SoC design flow requirements, and they adhere to DFX (Design for Test, Debug, Reliability, Manufacturing and Yield) requirements as defined by Arm.
You will use the IP Qualification flow along with the EDA tools from major providers.
You will analyze the deviations and share them with the SoC design teams for review and eventually report them to the IP providers for update.
As a senior engineer, you will propose and lead the implementation of new checks to improve the coverage and to better ensure the compliance of the receivables with SoC flow and DFX.