Principal FPGA Engineer

II-VI Incorporated•Horsham, PA

51d

About The Position

Primary Duties & Responsibilities FPGA Development for Layer 0 Photonic Line cards (EDFA and ROADM) - 60% Design using Coherent EDFA FPGA real time platform (aka OASIS) Interpret customer specifications and collaborate with firmware teams to design and implement solutions, including the FPGA top-level architecture. Design functional modules and provide detailed design documentation and register interface documentation. Perform coding and simulation. Conduct design verification, including FPGA logic validation and integration testing with firmware. Manage version release and maintain proper documentation. FPGA Development for Layer1 and System Products (Chassis, high-speed card) - 30% Select suitable FPGA/SoC solutions based on system requirements and design top-level architecture. Design functional modules and provide detailed design documentation and register interface documentation. Perform coding and simulation. Conduct design verification, including FPGA logic validation and integration testing with firmware. Manage version release and maintain proper documentation. Legacy Products Sustaining - 10% Develop new features based on customer requirements. Collaborate with cross functions to investigate field issues. Resolve FPGA issues in existing products.

Requirements

Bachelor's degree or higher in Electronic Engineering, Microelectronics Engineering, or related fields.
5+ years of experience in developing FPGA for communication or control system with Altera or Xilinx chips. Optical or Data communication industry experience is preferred.
Experience with FPGA SoC (NIOS2/ARM/RISC-V based) development, work closely to firmware team for better performance system design.
Experience with customized protocol design on various interfaces like PCIe, Ethernet, SPI, IIC, uart, etc
FPGA digital signal processing experience, e.g. low pass filter design and PID close-loop control.
Experience with lab bench debugging with oscilloscopes and logic analyzers.
Experience with Linux environment and python script for verification test.
Programming Languages: Verilog HDL, system Verilog, Python.
Experience with Altera FPGA/SoC, toolchain.
Experience with Xilinx FPGA/SoC, toolchain.
Experience with Lattice FPGA/CPLD and toolchain.
ModelSim simulation experience
Timing constraint and analysis.
Deliver to an aggressive schedule.
Self-starter, highly motivated, dedicated and teamwork oriented
Creative, analytical and structured problem solving capabilities.
Good inter-team communication skills

Nice To Haves

Optical or Data communication industry experience is preferred.

Responsibilities

FPGA Development for Layer 0 Photonic Line cards (EDFA and ROADM)
Design using Coherent EDFA FPGA real time platform (aka OASIS)
Interpret customer specifications and collaborate with firmware teams to design and implement solutions, including the FPGA top-level architecture.
Design functional modules and provide detailed design documentation and register interface documentation.
Perform coding and simulation.
Conduct design verification, including FPGA logic validation and integration testing with firmware.
Manage version release and maintain proper documentation.
FPGA Development for Layer1 and System Products (Chassis, high-speed card)
Select suitable FPGA/SoC solutions based on system requirements and design top-level architecture.
Develop new features based on customer requirements.
Collaborate with cross functions to investigate field issues.
Resolve FPGA issues in existing products.