Principal FPGA Design Engineer

SiTime Corporation • Santa Clara, CA

80d

About The Position

We are seeking a seasoned FPGA Architect with a minimum of 10 years of experience to lead the design and development of FPGA-based platforms that support internal testing and validation of our precision, high-performance MEMS timing products. This role is critical to developing robust infrastructure for frequency measurement, low phase noise and low jitter characterization, production, and system-level validation.

Requirements

• MS in Electrical Engineering, Computer Engineering, or related field
• 10+ years of hands-on experience in FPGA architecture and development (Xilinx, Intel/Altera, or similar)
• Deep expertise in Verilog/VHDL, simulation tools (ModelSim, Vivado, etc.), and scripting (Python, TCL)
• Proven track record in designing systems with low jitter, low phase noise, and high signal fidelity
• Strong understanding of timing analysis, clock domain crossing, and high-speed interfaces (PCIe, DDR, SERDES)
• Experience with lab bring-up, debugging tools (logic analyzers, oscilloscopes), and test automation
• Demonstrated leadership in driving cross-functional initiatives and delivering complex technical programs
• Excellent communication, collaboration, and stakeholder management skills

Nice To Haves

• Experience in MEMS or timing product domains
• Familiarity with hardware/software co-design and embedded systems
• Exposure to production test environments and ATE systems
• Experience presenting technical strategies and outcomes to executive leadership

Responsibilities

• Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing
• Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams
• Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains
• Own the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing closure, and bring-up
• Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure
• Champion design reviews, documentation standards, and continuous improvement practices
• Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs
• Act as a key technical liaison between engineering, product, and operations teams to ensure seamless integration and execution

Benefits

• 401k plan
• health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans
• quarterly bonus tied to the achievement of innovation goals
• equity grants

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Master's degree
• Number of Employees: 101-250 employees