Principal Engineer

Cadence Systems • San Jose, CA

8d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence – ASIC Design Verification - Job Description: ASIC/Processor Design Verification position Own all aspects of block/sub-system design-verification: test-plan creation/execution test-bench (all components) creation/enhancement/maintenance code/functional coverage Will be involved/interact with: post silicon validation/bring up/emulation teams

Requirements

• Strong expertise in building test-benches using: System-Verilog, UVM, C/C++
• Strong digital logic fundamentals and understanding
• Experience in functional coverage/code coverage/assertions (SVA) development and closure
• Experience in creating and maintaining executable test plans
• Strong debug skills
• Proficient in scripting/automation using any standard scripting language like Python etc.
• Excellent verbal and written communication skills and a good team player

Nice To Haves

• Emulation related experience will be a plus

Responsibilities

• test-plan creation/execution
• test-bench (all components) creation/enhancement/maintenance
• code/functional coverage

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed