Principal Engineer Position for System Power for Advanced 2.5D/3D High-Performance Compute
About The Position
Qualcomm Overview: Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform edge AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Job Overview: The Qualcomm Memory Design/Technology Team has an opening in the areas of System PDN and power modeling. The candidate will assess and optimize the high-performance chip and across-chiplet PDN architecture to ensure robust high-performance and low-noise compute. The candidate will assess the best use of on-die, backside, and chiplet interconnect resources to determine the best power grid with minimum overhead to the system fabrics such as high-bandwidth bus, compute cores, and low-noise high-speed IOs for applications spanning high-performance cloud, compute, mobile and IoT. The candidate will work on robust PDN solutions along with power modeling addressing reliability, noise, and performance requirements from PMIC, to the package, and on-die power rail. The candidate is expected to understand the concepts of power distribution network, decoupling capacitance, power integrity, and power modeling. This position offers the opportunity to work across multiple organizations such as process and packaging team, system power team, and global SoC team. Providing timely feedback and updating PDN architecture and design trade-offs to the team is essential.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Nice To Haves
- Master's or Ph.D. in Electrical Engineering or a related field
- Experience in PDN, optimal decoupling capacitance placement, and power modeling
- Experience in modeling resonances on chips and 2.5D systems through resistance, inductance, and capacitance extraction
- Good knowledge of signal and power integrity, and chiplets
- Good knowledge of in the modeling of interconnects, uBumps, TSVs, and package
- Good knowledge of cross-power domain structures, clamping, and ESD protection schemes
- Good knowledge of PMIC architecture, design, and noise modeling
- Proficiency in use of EDA tools such as Voltus, Redhawk, SPICE, Virtuoso
- Experience in circuit and system design to model the power architecture
- Experience in memory architecture power assessment
- Experience in model order reduction of large RLC networks
- Familiar with memory architecture
- Ability to develop IBIS/Verilog-A/Modeling models of power modeling is strong plus
- Familiar in thermal modeling and hotspot mitigation
- Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python)
- Familiar with high-frequency signal assessment
Responsibilities
- Develop and optimize PDN memory and computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W for mobile, compute, and XR applications
- Develop and validate models for power and power density modeling of multiple modules under different workloads
- Identify critical power scenarios and provide solutions within the constraints of packaging, floorplan, and PMIC module
- Develop PDN models in both time and frequency domain
- Simulate and emulate system power behavior on different power scenarios such as power-up, power-down, maximum performance, test/debug, and stand-by
- Identify locations of power switches and utilize optimal control mechanisms
- Floorplan 2.5/3D PDN under integration manufacturing constraints, testability, repairability, and high performance
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What This Job Offers
Job Type
Full-time
Career Level
Principal
