Principal Engineer, SI-PI

Cariad, Inc.•Mountain View, CA

3h•Hybrid

About The Position

The Principal Engineer, SI/PI (Signal Integrity / Power Integrity) is the electrical performance expert for CARIADs high-speed automotive compute platforms (infotainment, ADAS ECUs). This role's scope spans compute modules and carrier boards, high-speed connectors/cables, and return-path/grounding considerations from concept through EVT/DVT/PVT. The engineer ensures clean high-speed signaling and robust power delivery across PCB, package, and system interconnects to prevent noise, jitter, data errors, EMI failures, and system instability. The role involves influencing schematic and layout decisions early, building predictive models and simulations, and validating designs in the lab—partnering closely with SoC vendors, hardware/layout, EMC, and system validation teams to meet performance, EMC, and reliability targets.

Requirements

Technical leadership and systems-level thinking; able to influence design decisions across teams without direct authority.
Strong analytical and structured problem-solving skills; ability to diagnose complex electrical issues and drive closure.
Excellent communication skills (written, verbal, presentation) with ability to translate SI/PI findings into actionable design guidance.
Collaboration across global, cross-functional teams and suppliers; comfortable working across time zones.
High attention to detail and quality mindset; able to balance technical trade-offs across performance, cost, schedule, and manufacturability.
Deep experience with high-speed interfaces (e.g., PCIe, DDRx, Automotive Ethernet, MIPI/SerDes) and associated channel/receiver requirements.
Expertise in PCB stack-up, controlled-impedance routing, return-path design, via/connector modeling, and crosstalk/reflection mitigation.
Power delivery network (PDN) design and analysis including target impedance, decoupling strategy, VRM selection, and noise/droop control.
Hands-on simulation/modeling using SI/PI tools (e.g., Cadence Sigrity/SIwave, Keysight ADS, Ansys HFSS) and model types (S-parameters, IBIS-AMI, SPICE).
Lab proficiency with high-bandwidth oscilloscopes, TDR, VNA, probes/fixtures, and correlation of measurement to simulation.
Working knowledge of EMC/EMI principles as they relate to high-speed signaling, grounding, shielding, and power integrity in automotive ECUs.
12+ years of relevant experience in signal integrity/power integrity for high-speed digital systems (automotive, consumer electronics, or compute platforms).
Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or related field (or equivalent practical experience).

Nice To Haves

Experience bringing high-speed compute boards/ECUs through EVT/DVT/PVT and into production, including design rule governance and supplier reviews.
Experience with advanced packaging or module integration (SoC package escape, connector/cable assemblies, harness considerations).
Familiarity with automotive development and compliance constraints (e.g., EMC test cycles, reliability validation, AEC-Q component considerations).
Experience working with SoC vendors (e.g., Qualcomm, NVIDIA) on interface tuning, margining, and bring-up debug.
Background with scripting/automation for data analysis (Python, MATLAB) and reporting of SI/PI metrics.
Master’s degree or PhD in Electrical Engineering or a related discipline.

Responsibilities

Own channel budgets and SI sign-off reports per interface/program (margin targets, assumptions, and waiver rationale).
Analyze and optimize high-speed channels (PCIe, DDRx, Ethernet, MIPI/SerDes) for loss, crosstalk, reflections, jitter, and margin.
Define routing/topology guidelines (impedance, spacing, length matching, reference planes) and review PCB layouts for compliance.
Partner with architecture and board teams to drive interface trade-offs and risk reductions early in design.
Define PDN target-impedance specifications and PI sign-off reports per rail/domain (including transient/noise budgets).
Design and validate PDN across VRMs, planes, vias, and decoupling to meet target impedance and transient response goals.
Assess rail noise, droop/spike behavior, and coupling between power domains; recommend mitigation (placement, decaps, filters, sequencing).
Support power-up and load-step planning with system/SoC teams to ensure robust operation across use cases.
Maintain reusable SI/PI model library and simulation-to-measurement correlation reports; publish updated design rules/guard-bands.
Build and maintain SI/PI models (S-parameters, IBIS/IBIS-AMI, SPICE) and run what-if studies to predict risk before hardware build.
Use EM and circuit simulation tools (HFSS/SIwave/Sigrity/ADS or equivalents) to evaluate interconnects, packages, and planes.
Correlate simulation results to lab measurements and update models/rules to improve prediction accuracy.
Produce lab measurement and correlation reports (eye/jitter/BER, PDN impedance/noise) and support pre-compliance EMI/EMC debug as needed.
Perform characterization using oscilloscopes, TDR, VNA, high-speed probing, and automated margining where applicable.
Debug electrical issues during bring-up and validation, including intermittent errors, eye closure, power noise-induced faults, and pre-compliance EMI/EMC issues.
Document root cause, corrective actions, and verification evidence to support release readiness.
Own SI/PI sign-off checklist, waiver process, and 'golden' design-rule set; drive adoption across multiple boards/programs.
Lead design reviews and provide clear, actionable SI/PI sign-off criteria aligned with performance, EMC, and reliability targets.
Collaborate with EMC engineers to address emissions/susceptibility drivers tied to layout, grounding, shielding, and PDN behavior.
Mentor engineers and contribute to reusable design rules, checklists, and best-practice documentation across programs.