Principal Engineer, Hardware Systems & Silicon Validation

Marvell•Irvine, CA

42d

About The Position

The Post-Silicon Validation team is instrumental in designing test platforms and executing comprehensive validation processes that span functional, electrical, and system-level testing, along with firmware and software validation. The team also supports the integration of Marvell solutions into customer platforms, including Ethernet switches and Wi-Fi access points. System Validation Engineers ensure Marvell's connectivity products meet rigorous performance and reliability standards across enterprise, industrial, and cloud data center deployments. As a Principal Engineer in Hardware and Silicon Validation at Marvell, you will play a key role in the development and delivery of Marvell's Alaska-M and Alaska-C Ethernet PHY products. Your responsibilities will include validating high-performance networking hardware, such as copper 10GBASE-T Ethernet PHYs and high-speed PAM4 SERDES retimer transceivers-critical technologies that enable high-density Ethernet switch applications across enterprise, PoE, wireless, and data center environments.

Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Strong understanding of high-speed SERDES, equalization technique and Ethernet Networking protocols.
5+ years of experience with High Speed IO testing, Analog AFE characterization debugging and validation
Strong lab skills with hands on experience, in system bring up, system testing and debug.
In-depth working knowledge of test equipment used for PAM4 SERDES characterization and 10GBASE-T Cu PHY Ethernet AFE Analog ADC, DAC characterization (Scope, BERT, Network analyzer, Spectrum Analyser etc.).
Strong analytical, problem-solving and communication skills.

Nice To Haves

Working knowledge of Ethernet Networking interface and characterization.
Working knowledge and experience on Ethernet and PAM4 SERDES is a definite plus.
Extensive knowledge of the physical and protocol levels (PMA, PCS, MAC) of one or more common high-speed interfaces is an asset.
Working knowledge of hardware board design; able to read board schematics and board layout.
Working experience with Python.

Responsibilities

Own responsibility for Marvell Ethernet Cu PHY Validation in post-silicon environment.
Develop System-level and Silicon-level test plan for Marvell Alaska-M Ethernet PHY and Alaska-C HSC Retimer PHY products.
Define, document, execute and report the overall PHY validation/test plan for Marvell storage devices.
Lab-based silicon bring-up and unit test execution focused on 10BASE-T Physical and PCS layer hardware and firmware functionality.
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
Analyze and debug issues on PHY protocol of storage interface (SERDES, Ethernet).
Troubleshoot failing tests using diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
Lead collaborative technical discussions to drive resolution on technical issues. Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Cu PHY and High Speed SERDES Retimer PHY.
Work closely with customers to address design issue and debug failure cases.

Benefits

At Marvell, we offer a total compensation package with a base, bonus and equity.
Health and financial wellbeing are part of the package.
That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer.
Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

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