Principal Engineer, Design Verification

Analog Devices-posted 3 months ago
Full-time • Mid Level
Freer, SC
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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Analog Devices, Inc. (ADI) is seeking a Design Verification Engineer to join its CSS team, which focuses on leading the market in technology domains such as Capacitive Sensing, Optical Image Stabilization, Power management, and Audio. This role involves defining, developing, and implementing verification solutions for mixed signal ICs throughout the entire development cycle, from concept to product release. The position is based in Valencia, Spain or the United Kingdom (Edinburgh, Newbury) and offers the opportunity to collaborate with various business units within ADI, gaining exposure to multiple technologies and products.

  • Verification of complex designs and sub-systems using leading edge verification methodologies
  • Contribute to and influence decisions on methodologies/strategies for design verification
  • Develop testbench architectures using UVM or formal-based verification approaches
  • Define verification plans, functional coverage, tests, and verification methodology for block/chip-level verification
  • Work with the design team to generate verification plans and closure metrics
  • Debugging of Gate Level Simulation (GLS) and waiving Timing Violations approved by designer
  • Continuous interaction with analog co-sim and firmware team
  • Mentor and guide junior verification engineers on SoC Verification
  • Support post-silicon verification activities with design, product evaluation, and applications engineering teams
  • Lead verification efforts at IP or SoC level, including effort estimation, project scheduling, task assignment, and reporting to management or customers.
  • Bachelor's or master's degree in Engineering (Electronic Engineering) or equivalent
  • Experience in building and leading small verification teams
  • Strong interpersonal, teamwork, and communication skills
  • Self-motivated and enthusiastic with a strong level of English speaking and writing
  • Customer-facing experience as verification lead
  • Experience in both IP and SoC level verification
  • Strong knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion-based and formal verification techniques with System Verilog
  • Demonstrated experience in verification techniques for DSP/Processor subsystems or formal verification
  • Expert in developing unit and SoC level test benches using UVM
  • Excellent debugging and analytical skills
  • Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl
  • 10-15 years in ASIC design verification.
  • Experience with HW emulation or FPGA prototyping
  • Low power methodologies, e.g. UPF
  • Experience in behavioral modeling of analogue circuits
  • Experience in verifying processor-based designs
  • Knowledge of interface protocols e.g. AHB/APB/AXI/I2C/SPMI
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