Principal Engineer, Design Technology Co-optimization

Intel Corporation•Austin, TX

23h•Hybrid

About The Position

Organization Description Advanced Design & Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tie0/tie1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis is conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost. Job Role & Responsibility Description As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs. You will directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners. Your responsibility includes optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area, collaborating with EDA partners to optimize cell content in standard cell library to improve Intel technology entitlement at product level.

Requirements

Strong technical understanding of advanced semiconductor technology
Strong technical understanding of foundation IP design and design-technology co-optimization
Experience in standard cell library design with good understanding of MOSFET electrical characteristics, local layout effects, variability at advanced nodes
Experience with library cell characterization methodology and tools and Spice circuit simulations
Experience in semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective
Excellent oral and written communication skills
Collaborative mindset and great team player
Good track record of technical leadership and delivery
Ph.D. or master's degree in electrical engineering or computer science
10+ years of industry experience

Nice To Haves

Experience in product designs with good understanding of signoff methodology, tradeoffs across power, performance and tradeoff
Familiar with pre and post Si foundry benchmarking practices
Familiar with EDA tool design and optimization with experience in identification, design and verification of cells targeted to improve product level PPA
Experience in foundation IP Si validation

Responsibilities

driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs
directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners
optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area
collaborating with EDA partners to optimize cell content in standard cell library to improve Intel technology entitlement at product level