Tenstorrent-posted 4 months ago
$100,000 - $500,000/Yr
Full-time • Senior
501-1,000 employees

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement CPU system RTL. You’ll work to combine multiple cores, multiple clusters of cores, fabrics and subsystem components together, collaborating with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX, Fort Collins, CO or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

  • Define and implement CPU system RTL.
  • Combine multiple cores, multiple clusters of cores, fabrics and subsystem components.
  • Collaborate with DV, PD, architecture and performance teams to deliver a functional, timing, and power-converged design.
  • Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
  • Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
  • Enhance RTL design environment, tools, and methodologies to improve development efficiency.
  • 10+ years of industry experience with strong CPU systems RTL and microarchitecture background.
  • Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
  • Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
  • Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.
  • Highly competitive compensation package.
  • Base and variable compensation targets ranging from $100k - $500k.
  • Equal opportunity employer.
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