Principal Engineer, Automated Derivatives

Renesas Electronics • Austin, TX

1d • Hybrid

About The Position

In this multi-disciplinary role, you will lead the end-to-end delivery of derivative SoCs, focusing on the intersection of RTL design, functional verification, and physical implementation. You will not just execute flows; you will build an AI-augmented "Silicon Factory" that uses machine learning to bridge the gap between architectural intent and GDSII. Your goal is to achieve ultra-fast turnaround times by using AI to predict physical outcomes during RTL coding and to automate the verification of design variants.

Requirements

• Minimum of a Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
• 12–15 years of professional experience in the semiconductor industry, with a focus on Full-Stack Hardware Mastery, Physical Design Foundation, ML/AI Integration, Data-Driven Flow Dev, and Version Control & CI/CD.
• Proficiency in SystemVerilog for RTL design and UVM for functional verification.
• Solid understanding of Synthesis, P&R, and STA (Static Timing Analysis) to ensure RTL is physically realisable.
• Expert Python skills to build and deploy models that interface with both simulation tools (VCS, Xcelium) and implementation tools (Innovus, ICC2).
• Experience using Tcl/Python to extract "features" from simulation logs and implementation reports to train predictive models.
• Mastery of Git and CI/CD pipelines (Jenkins/GitLab) to manage the high-velocity deployment of design derivatives.

Responsibilities

• Use ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, reducing the number of "RTL-to-GDS" iterations.
• Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants.
• Employ AI to identify redundant logic or clock-gating opportunities to hit aggressive power targets in derivative designs.
• Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative (e.g., changed cache size or port count) is instantiated.
• Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, slashing simulation time and compute costs.
• Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data.
• Ensure a "zero-friction" path from RTL to Physical Design by using AI to automatically generate floorplan constraints and timing assertions from the design spec.
• Drive the physical implementation of derivatives, using AI to "reuse" placement and routing solutions from parent designs to achieve 10x faster convergence.

Benefits

• Launch and advance your career in technical and business roles across four Product Groups and various corporate functions.
• Opportunities to explore hardware and software capabilities and try new things.
• Make a real impact by developing innovative products and solutions to meet global customers' evolving needs and help make people’s lives easier, safe and secure.
• Maximize your performance and wellbeing in our flexible and inclusive work environment.
• People-first culture and global support system, including the remote work option and Employee Resource Groups.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 5,001-10,000 employees