Principal Embedded Software Engineer - Ethernet Retimers

Astera Labs•San Jose, CA

5h•$185,000 - $203,000•Onsite

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Our Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. As a Principal Engineer in our Signal Connectivity Engineering group, you'll contribute to firmware that directly impacts the performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams, you'll take ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity, you'll collaborate closely to bring these systems to production. We're a startup, and this role reflects that reality. You'll have responsibilities spanning firmware development, customer engagement, debug and validation support, and cross-functional coordination. We're looking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. Level is negotiable based on experience and qualifications. Location This is an on-site position based in our San Jose, CA office.

Requirements

BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field
10+ years of embedded C/C++ firmware development in resource-constrained environments
Deep understanding of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware design
Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices
Strong proficiency with Linux development tools: gcc/clang, make, bash scripting, gdb, and git
Excellent verbal and written communication skills; ability to explain complex technical concepts clearly
Demonstrated problem-solving ability and systematic debugging approach on real hardware
Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment

Nice To Haves

Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES
Familiarity with NIC or switch management software, for system test purposes
Exposure to SAI (Switch Abstraction Interface) or OpenBMC
Experience with Python for test automation, data analysis, or general scripting
Hands-on experience building and maintaining Jenkins CI/CD pipelines and automated test infrastructure
Background in retimer or gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity
Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar
Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin
Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments
Experience with RTOS, device drivers, or coroutines
Prior technical lead, mentorship, or team lead experience

Responsibilities

Develop and maintain embedded firmware for Ethernet retimers and gearboxes, from low-level hardware abstraction through customer-facing APIs
Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures
Support complex IP integration efforts across multiple subsystems within the SoC
Implement and optimize link training sequences, equalization tuning, and diagnostic features
Assist with software quality gates and validation criteria at each development phase
Partner with the software lead to drive product rollout activities from development through production deployment
Support customer integration efforts through firmware customization, debug assistance, and technical guidance
Investigate field-reported issues and coordinate resolution with internal teams
Develop and maintain SDK/API interfaces that enable customer platform integration
Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements
Collaborate with field applications engineers to support customer bring-up and resolve deployment issues
Partner with platform applications teams to ensure firmware meets system-level requirements
Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases
Provide regular project updates on progress, risks, dependencies, and technical challenges