Principal Digital ASIC Design Engineer

The Charles Stark Draper Laboratory-posted 14 days ago

$95,000 - $237,500/Yr

Full-time • Senior

Onsite • Cambridge, MA

1,001-5,000 employees

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Draper Laboratory is seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Senior Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies. You will be responsible for implementing designs from RTL through synthesis. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in different application areas.

Design and simulate circuits at transistor-level to implement architecture and requirement specifications
Contribute to system-level design
Optimize hardware designs for performance, power, and cost
Evaluate the hardware feasibility of complex algorithms and requirements
Independently contribute to complex chip architectures and designs
Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements
Contribute to business development and proposal activities
Develop, document, and teach best practices to less experienced engineers
Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics, contribute to design-for-test development.
Perform other duties as assigned

Proficiency in integrated circuit design
Understanding of integrated circuits, semiconductors, and general computer architecture
Ability to write detailed design specifications
Ability to lead multi-disciplinary technical teams
Excellent verbal and written communication skills
Excellent mathematical skills
Excellent organizational skills and attention to detail
Excellent time management skills with the proven ability to meet deadlines
Strong analytical and problem-solving skills
Ability to prioritize tasks
Demonstrate strong organization, planning, and time management skills to achieve program goals
Requires a bachelor's degree in Engineering, or related field. Masters degree preferred.
Requires 7-10 years of experience with a bachelor's degree, or 5-10 years of experience with a master's degree in ASIC Hardware Engineering or related.
Applicants should possess solid skills in front-end digital systems design with experience in design flows from Cadence or Synopsys.
Be fluent in System Verilog, Verilog or VHDL and familiar with LINT, simulation and synthesis.
Applicants selected for this position will be required to obtain and maintain a U.S. Security Clearance.

Experience with low power circuit design
Experience with CMOS advanced nodes below 32nm
Experience with radiation-hardened electronics
Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
Demonstrated experience with successful tape-outs at advanced nodes is desired.
Experience leading and managing design teams is also desired.

Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities.

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